Programming and Optimizing the Intel Knights Landing Manycore Processor
Time: 9:00 AM
Location: MIT-huset, Day 1: room MC313, Day 2: room MC413
The event is for: students - employees
This two days workshop is arranged together with PRACE, and will have instructors from Intel. The course focuses on programming and optimizing the Intel Knights Landing Manycore Processor. It addresses the Intel® Xeon Phi™, codenamed “Knights Landing (KNL)” architecture and how to best use it efficiently.
While the focus is on the KNL, the methods are applicable to many other architectures as well. The course is thus relevant to many different groups of people, including HPC users and researchers who want to get as much as possible possible out of their architecture. As well, the course is of interest for anyone who wants to increase their knowledge about vectorization and optimization, and learn more about how to apply it to their own codes.
Day 1 (KNL architecture, KNL configuration: memory and cluster modes, Intel® Software tools, exercises)
- 09:00-09:30 Introduction
- 09:30-10:30 Xeon Phi architecture (micro-architecture, cores, AVX512 instructions)
- 10:30-10:45 Coffee break
- 10:45-11:45 Hands-on (vectorization)
- 11:45-12:45 Lunch break
- 12:45-13:45 Xeon Phi configuration: memory and cluster modes
- 13:45-14:30 Hands-on (memory & cluster effect)
- 14:30-14:45 Coffee break
- 14:45-15:45 Intel® Software tools
- 15:45-16:45 Hands-on (Intel® tools on smaller examples)
- 16:45-17:15 Bring your own code
- 09:00-10:00 Porting on Xeon Phi. Case studies: Qr-mumps and smilei
- 10:00-10:45 Hands-on: bring your own code / continue working with the exercises.
- 10:45-11:00 Coffee break
- 11:00-12:00 Hands-on: bring your own code / continue working with the exercises.
- 12:00-13:00 Lunch break
- 13:00-14:45 Hands-on: bring your own code / continue working with the exercises.
- 14:45-15:00 Coffee break
- 15:00-15:30 Wrap-up